This invention relates generally to an integrated circuit used for receiving communication signals and, in particular, relates to an externally programmable integrated circuit used for acquiring and demodulating radio data communication signals.
Modern communication systems, such as Code Division Multiple Access and Time Divisional Multiple Access digital radio communication systems, are typically required to maintain low error rates at high data rates through radio paths that are subject to fading, multipath, and other RF impairments. It is also desirable in many applications to provide the radio receiver in a small, possibly portable package, that makes extensive use of integrated circuit technology.
An ability to provide certain radio receiver components in integrated circuit form is well known in the art. For example, in a data sheet entitled HSP43168 Dual FIR Filter, available from Harris Semiconductor (12/96), there is described a dual Finite Impulse Response (FIR) filter integrated circuit that is suitable for use in quadrature and complex filtering, adaptive filtering, polyphase filtering and image processing applications. The filter can be connected with a microprocessor and thereby programmed for use in an intended application.
It is a first object and advantage of this invention to provide an improved integrated circuit that embodies a dispersive channel receiver capable of rapidly acquiring a signal of interest.
It is a further object and advantage of this invention to provide an integrated circuit that comprises a reconfigurable FIR filter in combination with a coherent signal processor, a multi-ported coherent memory, a sequential weight processor, and a dual ported weight memory, all of which can be programmed during use for operating in one of a plurality of modes, including a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode.
The foregoing and other problems are overcome and the objects and advantages are realized by methods and apparatus in accordance with embodiments of this invention.
An integrated circuit in accordance with this invention includes a reconfigurable FIR filter that has an input port for receiving digital input signals and an output coupled to a coherent signal processor and a multi-ported coherent memory. The FIR filter programmably provides filtered signals to the coherent signal processor for storage in the coherent memory. The integrated circuit further includes a an adaptive sequential weight processor having an input coupled to an output port of the coherent memory. The sequential weight processor includes a weight memory and operates to output symbol soft decision data resulting from processing the digital input signals. The integrated circuit is programmable into one of a plurality of operating modes, including at least one of a received signal acquisition mode, a channel estimator mode, an adaptive equalizer mode, and a channel-wise differential mode. Polyphase operation is also within the capabilities of the integrated circuit. In the acquisition mode the FIR filter can be used, in combination with a weight ring and a weight mask, as a PN correlator.